[llvm] fix few copypaste typos

[klensy]

This looks like typos, but i don't understand code enough to be sure if it requires more fixes or not.

[llvmbot]

@llvm/pr-subscribers-llvm-transforms
@llvm/pr-subscribers-vectorizers

@llvm/pr-subscribers-backend-aarch64

Author: klensy (klensy)

Changes

This looks like typos, but i don't understand code enough to be sure if it requires more fixes or not.

---

Full diff: https://github.com/llvm/llvm-project/pull/119881.diff

3 Files Affected:

• (modified) llvm/lib/Target/AArch64/AArch64ISelLowering.cpp (+1-1)
• (modified) llvm/lib/Transforms/Scalar/JumpThreading.cpp (+1-1)
• (modified) llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp (+1-1)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 41e0214dab6c73..26a44904da92dc 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -18365,7 +18365,7 @@ static SDValue performUADDVAddCombine(SDValue A, SelectionDAG &DAG) {
     EVT VT = A.getValueType();
     SDValue Op0 = A.getOperand(0);
     SDValue Op1 = A.getOperand(1);
-    if (Op0.getOpcode() != Op0.getOpcode() ||
+    if (Op0.getOpcode() != Op1.getOpcode() ||
         (Op0.getOpcode() != ISD::ZERO_EXTEND &&
          Op0.getOpcode() != ISD::SIGN_EXTEND))
       return SDValue();
diff --git a/llvm/lib/Transforms/Scalar/JumpThreading.cpp b/llvm/lib/Transforms/Scalar/JumpThreading.cpp
index 16110cd25bc61c..e85b6e7f931785 100644
--- a/llvm/lib/Transforms/Scalar/JumpThreading.cpp
+++ b/llvm/lib/Transforms/Scalar/JumpThreading.cpp
@@ -2516,7 +2516,7 @@ void JumpThreadingPass::updateBlockFreqAndEdgeWeight(BasicBlock *PredBB,
                                                      BlockFrequencyInfo *BFI,
                                                      BranchProbabilityInfo *BPI,
                                                      bool HasProfile) {
-  assert(((BFI && BPI) || (!BFI && !BFI)) &&
+  assert(((BFI && BPI) || (!BFI && !BPI)) &&
          "Both BFI & BPI should either be set or unset");
 
   if (!BFI) {
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 0e11e8704db2f2..78a2de77c7fbae 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -13858,7 +13858,7 @@ class BoUpSLP::ShuffleInstructionBuilder final : public BaseShuffleAnalysis {
     Value *createShuffleVector(Value *V1, Value *V2, ArrayRef<int> Mask) {
       if (V1->getType() != V2->getType()) {
         assert(V1->getType()->isIntOrIntVectorTy() &&
-               V1->getType()->isIntOrIntVectorTy() &&
+               V2->getType()->isIntOrIntVectorTy() &&
                "Expected integer vector types only.");
         if (V1->getType() != V2->getType()) {
           if (cast<VectorType>(V2->getType())

[klensy]

This condition the same as outer if, should it be removed?

[alexey-bataev]

Yes, should be removed

[klensy]

llvm/test/Transforms/JumpThreading/select.ll test fails after change in JumpThreading.cpp, how should i change test?

[klensy]

Oh, there was already attempt in #95715, but pr stuck

[davemgreen]

The AArch64 part certainly does look wrong. We should add a test case and probably separate that out into a different review, to separate the different issues. Are you OK to do that, or are you happy for me to put it together?

Here's a test I came up with for it:

define i64 @add_v4i32_v4i64_zsext(<4 x i32> %xi) {
; CHECK-LABEL: add_v4i32_v4i64_zsext:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ushll v1.2d, v0.2s, #0
; CHECK-NEXT:    saddw2 v0.2d, v1.2d, v0.4s
; CHECK-NEXT:    addp d0, v0.2d
; CHECK-NEXT:    fmov x0, d0
; CHECK-NEXT:    ret
entry:
  %x = shufflevector <4 x i32> %xi, <4 x i32> %xi, <2 x i32> <i32 0, i32 1>
  %y = shufflevector <4 x i32> %xi, <4 x i32> %xi, <2 x i32> <i32 2, i32 3>
  %xx = zext <2 x i32> %x to <2 x i64>
  %yy = sext <2 x i32> %y to <2 x i64>
  %zz = add <2 x i64> %xx, %yy
  %z = call i64 @llvm.vector.reduce.add.v2i64(<2 x i64> %zz)
  ret i64 %z
}

[dtcxzyw]

Reverse ping.