[X86] Consistently use getVectorIdxConstant for element/subvector extract/insertion nodes. NFC. #123312
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…ract/insertion nodes. NFC. Avoid the use of getIntPtrConstant for anything other than address pointer related code. Noticed while trying to use getVectorIdxConstant as a breakpoint.
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@llvm/pr-subscribers-backend-x86 Author: Simon Pilgrim (RKSimon) ChangesAvoid the use of getIntPtrConstant for anything other than address pointer related code. Noticed while trying to use getVectorIdxConstant as a breakpoint. Patch is 64.38 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/123312.diff 1 Files Affected:
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 6d69665c17565a..e5437eeebe2f46 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -4079,7 +4079,7 @@ static SDValue extractSubVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG,
isNullConstant(Vec.getOperand(2)))
return DAG.getUNDEF(ResultVT);
- SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
+ SDValue VecIdx = DAG.getVectorIdxConstant(IdxVal, dl);
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
}
@@ -4123,7 +4123,7 @@ static SDValue insertSubVector(SDValue Result, SDValue Vec, unsigned IdxVal,
// we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
IdxVal &= ~(ElemsPerChunk - 1);
- SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
+ SDValue VecIdx = DAG.getVectorIdxConstant(IdxVal, dl);
return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
}
@@ -4161,7 +4161,7 @@ static SDValue widenSubVector(MVT VT, SDValue Vec, bool ZeroNewElements,
SDValue Res = ZeroNewElements ? getZeroVector(VT, Subtarget, DAG, dl)
: DAG.getUNDEF(VT);
return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, VT, Res, Vec,
- DAG.getIntPtrConstant(0, dl));
+ DAG.getVectorIdxConstant(0, dl));
}
/// Widen a vector to a larger size with the same scalar type, with the new
@@ -4492,7 +4492,7 @@ static SDValue insert1BitVector(SDValue Op, SelectionDAG &DAG,
MVT OpVT = Op.getSimpleValueType();
unsigned NumElems = OpVT.getVectorNumElements();
- SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
+ SDValue ZeroIdx = DAG.getVectorIdxConstant(0, dl);
// Extend to natively supported kshift.
MVT WideOpVT = widenMaskVectorType(OpVT, Subtarget);
@@ -6741,7 +6741,7 @@ static SDValue LowerBuildVectorAsInsert(SDValue Op, const SDLoc &DL,
}
}
V = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, V, Op.getOperand(i),
- DAG.getIntPtrConstant(i, DL));
+ DAG.getVectorIdxConstant(i, DL));
}
return V;
@@ -6823,7 +6823,7 @@ static SDValue LowerBuildVectorv16i8(SDValue Op, const SDLoc &DL,
}
Elt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Elt);
V = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, MVT::v8i16, V, Elt,
- DAG.getIntPtrConstant(i / 2, DL));
+ DAG.getVectorIdxConstant(i / 2, DL));
}
return DAG.getBitcast(MVT::v16i8, V);
@@ -6964,8 +6964,9 @@ static SDValue LowerBuildVectorv4x32(SDValue Op, const SDLoc &DL,
unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
- SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
- DAG.getIntPtrConstant(InsertPSMask, DL, true));
+ SDValue Result =
+ DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
+ DAG.getTargetConstant(InsertPSMask, DL, MVT::i8));
return DAG.getBitcast(VT, Result);
}
@@ -7285,7 +7286,7 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
DAG, Subtarget, IsAfterLegalize);
if (HalfLD)
return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT),
- HalfLD, DAG.getIntPtrConstant(0, DL));
+ HalfLD, DAG.getVectorIdxConstant(0, DL));
}
}
@@ -7820,7 +7821,7 @@ static SDValue buildFromShuffleMostly(SDValue Op, const SDLoc &DL,
for (unsigned Idx : InsertIndices)
NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
- DAG.getIntPtrConstant(Idx, DL));
+ DAG.getVectorIdxConstant(Idx, DL));
return NV;
}
@@ -7899,7 +7900,7 @@ static SDValue LowerBUILD_VECTORvXi1(SDValue Op, const SDLoc &dl,
MVT VecVT = VT.getSizeInBits() >= 8 ? VT : MVT::v8i1;
Select = DAG.getBitcast(VecVT, Select);
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Select,
- DAG.getIntPtrConstant(0, dl));
+ DAG.getVectorIdxConstant(0, dl));
}
}
@@ -7918,7 +7919,7 @@ static SDValue LowerBUILD_VECTORvXi1(SDValue Op, const SDLoc &dl,
MVT VecVT = VT.getSizeInBits() >= 8 ? VT : MVT::v8i1;
DstVec = DAG.getBitcast(VecVT, Imm);
DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, DstVec,
- DAG.getIntPtrConstant(0, dl));
+ DAG.getVectorIdxConstant(0, dl));
}
} else
DstVec = DAG.getUNDEF(VT);
@@ -7926,7 +7927,7 @@ static SDValue LowerBUILD_VECTORvXi1(SDValue Op, const SDLoc &dl,
for (unsigned InsertIdx : NonConstIdx) {
DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
Op.getOperand(InsertIdx),
- DAG.getIntPtrConstant(InsertIdx, dl));
+ DAG.getVectorIdxConstant(InsertIdx, dl));
}
return DstVec;
}
@@ -9384,7 +9385,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
for (unsigned i = 1; i < NumElems; ++i) {
if (Op.getOperand(i).isUndef()) continue;
Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
- Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
+ Op.getOperand(i), DAG.getVectorIdxConstant(i, dl));
}
return Result;
}
@@ -9479,7 +9480,7 @@ static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG,
Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec,
Op.getOperand(i),
- DAG.getIntPtrConstant(i * NumSubElems, dl));
+ DAG.getVectorIdxConstant(i * NumSubElems, dl));
}
return Vec;
@@ -9527,7 +9528,7 @@ static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
Op = DAG.getNode(X86ISD::KSHIFTL, dl, ShiftVT, Op,
DAG.getTargetConstant(Idx * SubVecNumElts, dl, MVT::i8));
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResVT, Op,
- DAG.getIntPtrConstant(0, dl));
+ DAG.getVectorIdxConstant(0, dl));
}
// If there are zero or one non-zeros we can handle this very simply.
@@ -9539,7 +9540,7 @@ static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
SDValue SubVec = Op.getOperand(Idx);
unsigned SubVecNumElts = SubVec.getSimpleValueType().getVectorNumElements();
return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, SubVec,
- DAG.getIntPtrConstant(Idx * SubVecNumElts, dl));
+ DAG.getVectorIdxConstant(Idx * SubVecNumElts, dl));
}
if (NumOperands > 2) {
@@ -9559,9 +9560,9 @@ static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
SDValue Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT,
DAG.getUNDEF(ResVT), Op.getOperand(0),
- DAG.getIntPtrConstant(0, dl));
+ DAG.getVectorIdxConstant(0, dl));
return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Vec, Op.getOperand(1),
- DAG.getIntPtrConstant(NumElems/2, dl));
+ DAG.getVectorIdxConstant(NumElems/2, dl));
}
static SDValue LowerCONCAT_VECTORS(SDValue Op,
@@ -12726,7 +12727,7 @@ static SDValue lowerShuffleOfExtractsAsVperm(const SDLoc &DL, SDValue N0,
NewMask);
// This is free: ymm -> xmm.
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Shuf,
- DAG.getIntPtrConstant(0, DL));
+ DAG.getVectorIdxConstant(0, DL));
}
/// Try to lower broadcast of a single element.
@@ -15256,10 +15257,10 @@ static SDValue lowerV2X128Shuffle(const SDLoc &DL, MVT VT, SDValue V1,
if (WidenedMask[0] == 0 && IsHighZero) {
MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(), 2);
SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
- DAG.getIntPtrConstant(0, DL));
+ DAG.getVectorIdxConstant(0, DL));
return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
getZeroVector(VT, Subtarget, DAG, DL), LoV,
- DAG.getIntPtrConstant(0, DL));
+ DAG.getVectorIdxConstant(0, DL));
}
// TODO: If minimizing size and one of the inputs is a zero vector and the
@@ -15283,11 +15284,11 @@ static SDValue lowerV2X128Shuffle(const SDLoc &DL, MVT VT, SDValue V1,
// this will likely become vinsertf128 which can't fold a 256-bit memop.
if (!isa<LoadSDNode>(peekThroughBitcasts(V1))) {
MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(), 2);
- SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
- OnlyUsesV1 ? V1 : V2,
- DAG.getIntPtrConstant(0, DL));
+ SDValue SubVec =
+ DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, OnlyUsesV1 ? V1 : V2,
+ DAG.getVectorIdxConstant(0, DL));
return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, V1, SubVec,
- DAG.getIntPtrConstant(2, DL));
+ DAG.getVectorIdxConstant(2, DL));
}
}
@@ -15580,7 +15581,7 @@ static SDValue getShuffleHalfVectors(const SDLoc &DL, SDValue V1, SDValue V2,
SDValue V = (HalfIdx < 2 ? V1 : V2);
HalfIdx = (HalfIdx % 2) * HalfNumElts;
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V,
- DAG.getIntPtrConstant(HalfIdx, DL));
+ DAG.getVectorIdxConstant(HalfIdx, DL));
};
// ins undef, (shuf (ext V1, HalfIdx1), (ext V2, HalfIdx2), HalfMask), Offset
@@ -15597,7 +15598,7 @@ static SDValue getShuffleHalfVectors(const SDLoc &DL, SDValue V1, SDValue V2,
unsigned Offset = UndefLower ? HalfNumElts : 0;
return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), V,
- DAG.getIntPtrConstant(Offset, DL));
+ DAG.getVectorIdxConstant(Offset, DL));
}
/// Lower shuffles where an entire half of a 256 or 512-bit vector is UNDEF.
@@ -15624,9 +15625,9 @@ static SDValue lowerShuffleWithUndefHalf(const SDLoc &DL, MVT VT, SDValue V1,
if (!UndefLower &&
isSequentialOrUndefInRange(Mask, 0, HalfNumElts, HalfNumElts)) {
SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V1,
- DAG.getIntPtrConstant(HalfNumElts, DL));
+ DAG.getVectorIdxConstant(HalfNumElts, DL));
return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), Hi,
- DAG.getIntPtrConstant(0, DL));
+ DAG.getVectorIdxConstant(0, DL));
}
// Lower half is undef and upper half is whole lower subvector.
@@ -15634,9 +15635,9 @@ static SDValue lowerShuffleWithUndefHalf(const SDLoc &DL, MVT VT, SDValue V1,
if (UndefLower &&
isSequentialOrUndefInRange(Mask, HalfNumElts, HalfNumElts, 0)) {
SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V1,
- DAG.getIntPtrConstant(0, DL));
+ DAG.getVectorIdxConstant(0, DL));
return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), Hi,
- DAG.getIntPtrConstant(HalfNumElts, DL));
+ DAG.getVectorIdxConstant(HalfNumElts, DL));
}
int HalfIdx1, HalfIdx2;
@@ -16019,7 +16020,7 @@ static SDValue lowerShuffleAsVTRUNCAndUnpack(const SDLoc &DL, MVT VT,
// Insert the unpckldq into a zero vector to widen to v32i8.
return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v32i8,
DAG.getConstant(0, DL, MVT::v32i8), Unpack,
- DAG.getIntPtrConstant(0, DL));
+ DAG.getVectorIdxConstant(0, DL));
}
// a = shuffle v1, v2, mask1 ; interleaving lower lanes of v1 and v2
@@ -16948,10 +16949,10 @@ static SDValue lowerV4X128Shuffle(const SDLoc &DL, MVT VT, ArrayRef<int> Mask,
unsigned NumElts = ((Zeroable & 0x0c) == 0x0c) ? 2 : 4;
MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(), NumElts);
SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
- DAG.getIntPtrConstant(0, DL));
+ DAG.getVectorIdxConstant(0, DL));
return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
getZeroVector(VT, Subtarget, DAG, DL), LoV,
- DAG.getIntPtrConstant(0, DL));
+ DAG.getVectorIdxConstant(0, DL));
}
// Check for patterns which can be matched with a single insert of a 256-bit
@@ -16962,9 +16963,9 @@ static SDValue lowerV4X128Shuffle(const SDLoc &DL, MVT VT, ArrayRef<int> Mask,
MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(), 4);
SDValue SubVec =
DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, OnlyUsesV1 ? V1 : V2,
- DAG.getIntPtrConstant(0, DL));
+ DAG.getVectorIdxConstant(0, DL));
return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, V1, SubVec,
- DAG.getIntPtrConstant(4, DL));
+ DAG.getVectorIdxConstant(4, DL));
}
// See if this is an insertion of the lower 128-bits of V2 into V1.
@@ -16993,7 +16994,7 @@ static SDValue lowerV4X128Shuffle(const SDLoc &DL, MVT VT, ArrayRef<int> Mask,
if (IsInsert && V2Index >= 0) {
MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(), 2);
SDValue Subvec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
- DAG.getIntPtrConstant(0, DL));
+ DAG.getVectorIdxConstant(0, DL));
return insert128BitVector(V1, Subvec, V2Index * 2, DAG, DL);
}
@@ -17600,7 +17601,7 @@ static SDValue lower1BitShuffleAsKSHIFTR(const SDLoc &DL, ArrayRef<int> Mask,
Res = DAG.getNode(X86ISD::KSHIFTR, DL, Res.getValueType(), Res,
DAG.getTargetConstant(ShiftAmt, DL, MVT::i8));
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res,
- DAG.getIntPtrConstant(0, DL));
+ DAG.getVectorIdxConstant(0, DL));
}
// Determine if this shuffle can be implemented with a KSHIFT instruction.
@@ -17678,10 +17679,10 @@ static SDValue lower1BitShuffle(const SDLoc &DL, ArrayRef<int> Mask,
MVT ExtractVT = MVT::getVectorVT(MVT::i1, SubvecElts);
SDValue Extract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ExtractVT,
Src == 0 ? V1 : V2,
- DAG.getIntPtrConstant(0, DL));
+ DAG.getVectorIdxConstant(0, DL));
return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
DAG.getConstant(0, DL, VT),
- Extract, DAG.getIntPtrConstant(0, DL));
+ Extract, DAG.getVectorIdxConstant(0, DL));
}
// Try a simple shift right with undef elements. Later we'll try with zeros.
@@ -17710,7 +17711,7 @@ static SDValue lower1BitShuffle(const SDLoc &DL, ArrayRef<int> Mask,
Res = DAG.getNode(Opcode, DL, WideVT, Res,
DAG.getTargetConstant(ShiftAmt, DL, MVT::i8));
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res,
- DAG.getIntPtrConstant(0, DL));
+ DAG.getVectorIdxConstant(0, DL));
}
Offset += NumElts; // Increment for next iteration.
}
@@ -18336,7 +18337,7 @@ static SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG,
DAG.getTargetConstant(IdxVal, dl, MVT::i8));
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
- DAG.getIntPtrConstant(0, dl));
+ DAG.getVectorIdxConstant(0, dl));
}
// Helper to find all the extracted elements from a vector.
@@ -18435,7 +18436,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
// this can be done with a mask.
IdxVal &= ElemsPerChunk - 1;
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
- DAG.getIntPtrConstant(IdxVal, dl));
+ DAG.getVectorIdxConstant(IdxVal, dl));
}
assert(VecVT.is128BitVector() && "Unexpected vector length");
@@ -18476,7 +18477,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
if (DWordIdx == 0 && DemandedElts == (DemandedElts & 15)) {
SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
DAG.getBitcast(MVT::v4i32, Vec),
- DAG.getIntPtrConstant(DWordIdx, dl));
+ DAG.getVectorIdxConstant(DWordIdx, dl));
int ShiftVal = (IdxVal % 4) * 8;
if (ShiftVal != 0)
Res = DAG.getNode(ISD::SRL, dl, MVT::i32, Res,
@@ -18488,7 +18489,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
if (DemandedElts == (DemandedElts & (3 << (WordIdx * 2)))) {
SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
DAG.getBitcast(MVT::v8i16, Vec),
- DAG.getIntPtrConstant(WordIdx, dl));
+ DAG.getVectorIdxConstant(WordIdx, dl));
int ShiftVal = (IdxVal % 2) * 8;
if (ShiftVal != 0)
Res = DAG.getNode(ISD::SRL, dl, MVT::i16, Res,
@@ -18506,7 +18507,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
Mask[0] = static_cast<int>(IdxVal);
Vec = DAG.getVectorShuffle(VecVT, dl, Vec, DAG.getUNDEF(VecVT), Mask);
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
- DAG.getIntPtrConstant(0, dl));
+ DAG.getVectorIdxConstant(0, dl));
}
if (VT.getSizeInBits() == 64) {
@@ -18522,7 +18523,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
int Mask[2] = { 1, -1 };
Vec = DAG.getVectorShuffle(VecVT, dl, Vec, DAG.getUNDEF(VecVT), Mask);
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
- DAG.getIntPtrConstant(0, dl));
+ DAG.getVectorIdxConstant(0, dl));
}
return SDValue();
@@ -18683,7 +18684,7 @@ SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1);
V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
- DAG.getIntPtrConstant(IdxIn128, dl));
+ DAG.getVectorIdxConstant(IdxIn128, dl));
// Insert the changed part back into the bigger vector
return insert128BitVector(N0, V, IdxVal, DAG, dl);
@@ -18832,7 +18833,7 @@ static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget &Subtarget,
DAG.getTargetConstant(IdxVal, dl, MVT::i8));
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, Op.getValueType(), Vec,
- DAG.getIntPtrConstant(0, dl));
+ DAG.getVectorIdxConstant(0, dl));
}
// Returns the appropriate wrapper opcode for a global reference.
@@ -19414,14 +19415,14 @@ static SDValue LowerI64IntToFP_AVX512DQ(SDValue Op, const SDLoc &dl,
{Op.getOperand(0), InVec});
SDValue Chain = CvtVec.getValue(1);
SDValue Value = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, CvtVec,
- DAG.getIntPtrConstant(0, dl));
+ DAG.getVectorIdxConstant(0, dl));
return DAG.getMergeValues({Value, Chain}, dl);
}
SDValue CvtVec = DAG.getNode(Op.getOpcode(), dl, VecVT, InVec);
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, CvtVec,
- DAG.getIntPtrConstant(0, dl));
+ DAG.getVectorIdxConstant(0, dl));
}
// Try to use a packed vector operation to handle i64 on 32-bit targets.
@@ -19450,14 +19451,14 @@ static SDValue LowerI64IntToFP16(SDValue Op, const SDLoc &dl, SelectionDAG &DAG,
{Op.getOperand(0), InVec});
SDValue Chain = CvtVec.getValue(1);
SDValue Value = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, CvtVec,
- DAG.getIntPtrConstant(0, dl));
+ DAG.getVectorIdxConstan...
[truncated]
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✅ With the latest revision this PR passed the C/C++ code formatter. |
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Avoid the use of getIntPtrConstant for anything other than address pointer related code.
Noticed while trying to use getVectorIdxConstant as a breakpoint.