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Merged
merged 3 commits into from
Mar 6, 2025
Merged

[AMDGPU] Masked load vectortype test #129703

merged 3 commits into from
Mar 6, 2025

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JanekvO
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@JanekvO JanekvO commented Mar 4, 2025

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@JanekvO JanekvO requested a review from arsenm March 4, 2025 13:19
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llvmbot commented Mar 4, 2025

@llvm/pr-subscribers-backend-amdgpu

Author: Janek van Oirschot (JanekvO)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/129703.diff

1 Files Affected:

  • (added) llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll (+255)
diff --git a/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll b/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
new file mode 100644
index 0000000000000..55da31eea05b4
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
@@ -0,0 +1,255 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck --check-prefix=GFX942 %s
+
+define <2 x i32> @masked_load_v2i32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) {
+; GFX942-LABEL: masked_load_v2i32:
+; GFX942:       ; %bb.0: ; %entry
+; GFX942-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX942-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX942-NEXT:    v_mov_b32_e32 v0, 0
+; GFX942-NEXT:    v_mov_b32_e32 v1, v0
+; GFX942-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX942-NEXT:    s_cbranch_execz .LBB0_2
+; GFX942-NEXT:  ; %bb.1: ; %cond.load
+; GFX942-NEXT:    global_load_dwordx2 v[0:1], v0, s[0:1]
+; GFX942-NEXT:  .LBB0_2:
+; GFX942-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX942-NEXT:    s_waitcnt vmcnt(0)
+; GFX942-NEXT:    s_setpc_b64 s[30:31]
+entry:
+  %0 = insertelement <2 x i1> poison, i1 %mask, i64 0
+  %1 = shufflevector <2 x i1> %0, <2 x i1> poison, <2 x i32> zeroinitializer
+  %result = tail call <2 x i32> @llvm.masked.load.v2i32.p1(ptr addrspace(1) %ptr, i32 2, <2 x i1> %1, <2 x i32> zeroinitializer)
+  ret <2 x i32> %result
+}
+
+define <4 x i32> @masked_load_v4i32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) {
+; GFX942-LABEL: masked_load_v4i32:
+; GFX942:       ; %bb.0: ; %entry
+; GFX942-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX942-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX942-NEXT:    v_mov_b32_e32 v0, 0
+; GFX942-NEXT:    v_mov_b32_e32 v1, v0
+; GFX942-NEXT:    v_mov_b32_e32 v2, v0
+; GFX942-NEXT:    v_mov_b32_e32 v3, v0
+; GFX942-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX942-NEXT:    s_cbranch_execz .LBB1_2
+; GFX942-NEXT:  ; %bb.1: ; %cond.load
+; GFX942-NEXT:    global_load_dwordx4 v[0:3], v0, s[0:1]
+; GFX942-NEXT:  .LBB1_2:
+; GFX942-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX942-NEXT:    s_waitcnt vmcnt(0)
+; GFX942-NEXT:    s_setpc_b64 s[30:31]
+entry:
+  %0 = insertelement <4 x i1> poison, i1 %mask, i64 0
+  %1 = shufflevector <4 x i1> %0, <4 x i1> poison, <4 x i32> zeroinitializer
+  %result = tail call <4 x i32> @llvm.masked.load.v4i32.p1(ptr addrspace(1) %ptr, i32 4, <4 x i1> %1, <4 x i32> zeroinitializer)
+  ret <4 x i32> %result
+}
+
+define <4 x float> @masked_load_v4f32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) {
+; GFX942-LABEL: masked_load_v4f32:
+; GFX942:       ; %bb.0: ; %entry
+; GFX942-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX942-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX942-NEXT:    v_mov_b32_e32 v0, 0
+; GFX942-NEXT:    v_mov_b32_e32 v1, v0
+; GFX942-NEXT:    v_mov_b32_e32 v2, v0
+; GFX942-NEXT:    v_mov_b32_e32 v3, v0
+; GFX942-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX942-NEXT:    s_cbranch_execz .LBB2_2
+; GFX942-NEXT:  ; %bb.1: ; %cond.load
+; GFX942-NEXT:    global_load_dwordx4 v[0:3], v0, s[0:1]
+; GFX942-NEXT:  .LBB2_2:
+; GFX942-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX942-NEXT:    s_waitcnt vmcnt(0)
+; GFX942-NEXT:    s_setpc_b64 s[30:31]
+entry:
+  %0 = insertelement <4 x i1> poison, i1 %mask, i64 0
+  %1 = shufflevector <4 x i1> %0, <4 x i1> poison, <4 x i32> zeroinitializer
+  %result = tail call <4 x float> @llvm.masked.load.v4f32.p1(ptr addrspace(1) %ptr, i32 4, <4 x i1> %1, <4 x float> zeroinitializer)
+  ret <4 x float> %result
+}
+
+define <8 x i32> @masked_load_v8i32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) {
+; GFX942-LABEL: masked_load_v8i32:
+; GFX942:       ; %bb.0: ; %entry
+; GFX942-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX942-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX942-NEXT:    v_mov_b32_e32 v0, 0
+; GFX942-NEXT:    v_mov_b32_e32 v1, v0
+; GFX942-NEXT:    v_mov_b32_e32 v2, v0
+; GFX942-NEXT:    v_mov_b32_e32 v3, v0
+; GFX942-NEXT:    v_mov_b32_e32 v4, v0
+; GFX942-NEXT:    v_mov_b32_e32 v5, v0
+; GFX942-NEXT:    v_mov_b32_e32 v6, v0
+; GFX942-NEXT:    v_mov_b32_e32 v7, v0
+; GFX942-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX942-NEXT:    s_cbranch_execz .LBB3_2
+; GFX942-NEXT:  ; %bb.1: ; %cond.load
+; GFX942-NEXT:    global_load_dwordx4 v[4:7], v0, s[0:1] offset:16
+; GFX942-NEXT:    s_nop 0
+; GFX942-NEXT:    global_load_dwordx4 v[0:3], v0, s[0:1]
+; GFX942-NEXT:  .LBB3_2:
+; GFX942-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX942-NEXT:    s_waitcnt vmcnt(0)
+; GFX942-NEXT:    s_setpc_b64 s[30:31]
+entry:
+  %0 = insertelement <8 x i1> poison, i1 %mask, i64 0
+  %1 = shufflevector <8 x i1> %0, <8 x i1> poison, <8 x i32> zeroinitializer
+  %result = tail call <8 x i32> @llvm.masked.load.v8i32.p1(ptr addrspace(1) %ptr, i32 4, <8 x i1> %1, <8 x i32> zeroinitializer)
+  ret <8 x i32> %result
+}
+
+define <8 x float> @masked_load_v8f32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) {
+; GFX942-LABEL: masked_load_v8f32:
+; GFX942:       ; %bb.0: ; %entry
+; GFX942-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX942-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX942-NEXT:    v_mov_b32_e32 v0, 0
+; GFX942-NEXT:    v_mov_b32_e32 v1, v0
+; GFX942-NEXT:    v_mov_b32_e32 v2, v0
+; GFX942-NEXT:    v_mov_b32_e32 v3, v0
+; GFX942-NEXT:    v_mov_b32_e32 v4, v0
+; GFX942-NEXT:    v_mov_b32_e32 v5, v0
+; GFX942-NEXT:    v_mov_b32_e32 v6, v0
+; GFX942-NEXT:    v_mov_b32_e32 v7, v0
+; GFX942-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX942-NEXT:    s_cbranch_execz .LBB4_2
+; GFX942-NEXT:  ; %bb.1: ; %cond.load
+; GFX942-NEXT:    global_load_dwordx4 v[4:7], v0, s[0:1] offset:16
+; GFX942-NEXT:    s_nop 0
+; GFX942-NEXT:    global_load_dwordx4 v[0:3], v0, s[0:1]
+; GFX942-NEXT:  .LBB4_2:
+; GFX942-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX942-NEXT:    s_waitcnt vmcnt(0)
+; GFX942-NEXT:    s_setpc_b64 s[30:31]
+entry:
+  %0 = insertelement <8 x i1> poison, i1 %mask, i64 0
+  %1 = shufflevector <8 x i1> %0, <8 x i1> poison, <8 x i32> zeroinitializer
+  %result = tail call <8 x float> @llvm.masked.load.v8f32.p1(ptr addrspace(1) %ptr, i32 4, <8 x i1> %1, <8 x float> zeroinitializer)
+  ret <8 x float> %result
+}
+
+define <8 x i16> @masked_load_v8i16(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) {
+; GFX942-LABEL: masked_load_v8i16:
+; GFX942:       ; %bb.0: ; %entry
+; GFX942-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX942-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX942-NEXT:    v_mov_b32_e32 v0, 0
+; GFX942-NEXT:    v_mov_b32_e32 v1, v0
+; GFX942-NEXT:    v_mov_b32_e32 v2, v0
+; GFX942-NEXT:    v_mov_b32_e32 v3, v0
+; GFX942-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX942-NEXT:    s_cbranch_execz .LBB5_2
+; GFX942-NEXT:  ; %bb.1: ; %cond.load
+; GFX942-NEXT:    global_load_dwordx4 v[0:3], v0, s[0:1]
+; GFX942-NEXT:  .LBB5_2:
+; GFX942-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX942-NEXT:    s_waitcnt vmcnt(0)
+; GFX942-NEXT:    s_setpc_b64 s[30:31]
+entry:
+  %0 = insertelement <8 x i1> poison, i1 %mask, i16 0
+  %1 = shufflevector <8 x i1> %0, <8 x i1> poison, <8 x i32> zeroinitializer
+  %result = tail call <8 x i16> @llvm.masked.load.v8i16.p1(ptr addrspace(1) %ptr, i32 4, <8 x i1> %1, <8 x i16> zeroinitializer)
+  ret <8 x i16> %result
+}
+
+define <8 x half> @masked_load_v8f16(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) {
+; GFX942-LABEL: masked_load_v8f16:
+; GFX942:       ; %bb.0: ; %entry
+; GFX942-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX942-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX942-NEXT:    v_mov_b32_e32 v0, 0
+; GFX942-NEXT:    v_mov_b32_e32 v1, v0
+; GFX942-NEXT:    v_mov_b32_e32 v2, v0
+; GFX942-NEXT:    v_mov_b32_e32 v3, v0
+; GFX942-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX942-NEXT:    s_cbranch_execz .LBB6_2
+; GFX942-NEXT:  ; %bb.1: ; %cond.load
+; GFX942-NEXT:    global_load_dwordx4 v[0:3], v0, s[0:1]
+; GFX942-NEXT:  .LBB6_2:
+; GFX942-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX942-NEXT:    s_waitcnt vmcnt(0)
+; GFX942-NEXT:    s_setpc_b64 s[30:31]
+entry:
+  %0 = insertelement <8 x i1> poison, i1 %mask, i16 0
+  %1 = shufflevector <8 x i1> %0, <8 x i1> poison, <8 x i32> zeroinitializer
+  %result = tail call <8 x half> @llvm.masked.load.v8f16.p1(ptr addrspace(1) %ptr, i32 4, <8 x i1> %1, <8 x half> zeroinitializer)
+  ret <8 x half> %result
+}
+
+define <8 x bfloat> @masked_load_v8bf16(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) {
+; GFX942-LABEL: masked_load_v8bf16:
+; GFX942:       ; %bb.0: ; %entry
+; GFX942-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX942-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX942-NEXT:    v_mov_b32_e32 v0, 0
+; GFX942-NEXT:    v_mov_b32_e32 v1, v0
+; GFX942-NEXT:    v_mov_b32_e32 v2, v0
+; GFX942-NEXT:    v_mov_b32_e32 v3, v0
+; GFX942-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX942-NEXT:    s_cbranch_execz .LBB7_2
+; GFX942-NEXT:  ; %bb.1: ; %cond.load
+; GFX942-NEXT:    global_load_dwordx4 v[0:3], v0, s[0:1]
+; GFX942-NEXT:  .LBB7_2:
+; GFX942-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX942-NEXT:    s_waitcnt vmcnt(0)
+; GFX942-NEXT:    s_setpc_b64 s[30:31]
+entry:
+ %0 = insertelement <8 x i1> poison, i1 %mask, i32 0
+ %1 = shufflevector <8 x i1> %0, <8 x i1> poison, <8 x i32> zeroinitializer
+ %result = tail call <8 x bfloat> @llvm.masked.load.v8bf16.p1(ptr addrspace(1) %ptr, i32 4, <8 x i1> %1, <8 x bfloat> zeroinitializer)
+ ret <8 x bfloat> %result
+}
+
+define <16 x i8> @masked_load_v16i8(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) {
+; GFX942-LABEL: masked_load_v16i8:
+; GFX942:       ; %bb.0: ; %entry
+; GFX942-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX942-NEXT:    v_and_b32_e32 v0, 1, v0
+; GFX942-NEXT:    v_mov_b32_e32 v16, 0
+; GFX942-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
+; GFX942-NEXT:    v_mov_b32_e32 v17, v16
+; GFX942-NEXT:    v_mov_b32_e32 v18, v16
+; GFX942-NEXT:    v_mov_b32_e32 v19, v16
+; GFX942-NEXT:    s_and_saveexec_b64 s[2:3], vcc
+; GFX942-NEXT:    s_cbranch_execz .LBB8_2
+; GFX942-NEXT:  ; %bb.1: ; %cond.load
+; GFX942-NEXT:    global_load_dwordx4 v[16:19], v16, s[0:1]
+; GFX942-NEXT:  .LBB8_2:
+; GFX942-NEXT:    s_or_b64 exec, exec, s[2:3]
+; GFX942-NEXT:    s_waitcnt vmcnt(0)
+; GFX942-NEXT:    v_lshrrev_b64 v[20:21], 24, v[16:17]
+; GFX942-NEXT:    v_lshrrev_b64 v[22:23], 24, v[18:19]
+; GFX942-NEXT:    v_lshrrev_b32_e32 v1, 8, v16
+; GFX942-NEXT:    v_lshrrev_b32_e32 v2, 16, v16
+; GFX942-NEXT:    v_lshrrev_b32_e32 v5, 8, v17
+; GFX942-NEXT:    v_lshrrev_b32_e32 v6, 16, v17
+; GFX942-NEXT:    v_lshrrev_b32_e32 v7, 24, v17
+; GFX942-NEXT:    v_lshrrev_b32_e32 v9, 8, v18
+; GFX942-NEXT:    v_lshrrev_b32_e32 v10, 16, v18
+; GFX942-NEXT:    v_lshrrev_b32_e32 v13, 8, v19
+; GFX942-NEXT:    v_lshrrev_b32_e32 v14, 16, v19
+; GFX942-NEXT:    v_lshrrev_b32_e32 v15, 24, v19
+; GFX942-NEXT:    v_mov_b32_e32 v0, v16
+; GFX942-NEXT:    v_mov_b32_e32 v3, v20
+; GFX942-NEXT:    v_mov_b32_e32 v4, v17
+; GFX942-NEXT:    v_mov_b32_e32 v8, v18
+; GFX942-NEXT:    v_mov_b32_e32 v11, v22
+; GFX942-NEXT:    v_mov_b32_e32 v12, v19
+; GFX942-NEXT:    s_setpc_b64 s[30:31]
+entry:
+ %0 = insertelement <16 x i1> poison, i1 %mask, i32 0
+ %1 = shufflevector <16 x i1> %0, <16 x i1> poison, <16 x i32> zeroinitializer
+ %result = tail call <16 x i8> @llvm.masked.load.v16i8.p1(ptr addrspace(1) %ptr, i32 4, <16 x i1> %1, <16 x i8> zeroinitializer)
+ ret <16 x i8> %result
+}

@JanekvO JanekvO mentioned this pull request Mar 4, 2025
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arsenm
arsenm reviewed Mar 5, 2025
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llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll Outdated
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck --check-prefix=GFX942 %s

define <2 x i32> @masked_load_ptr1_mask_v2i32(ptr addrspace(1) inreg nocapture readonly %ptr, i1 %mask) {
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can you add something to the name to indicate which are uniform and which are divergent? These are all using uniform base pointers

@JanekvO JanekvO merged commit cc98b35 into llvm:main Mar 6, 2025
11 checks passed
@JanekvO JanekvO deleted the precommit-masked-load-vectortype-test branch March 6, 2025 17:02
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llvm-ci commented Mar 6, 2025

LLVM Buildbot has detected a new failure on builder ml-opt-devrel-x86-64 running on ml-opt-devrel-x86-64-b1 while building llvm at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/175/builds/14392

Here is the relevant piece of the build log for the reference 
Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/AMDGPU/masked-load-vectortypes.ll' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 2: /b/ml-opt-devrel-x86-64-b1/build/bin/llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll | /b/ml-opt-devrel-x86-64-b1/build/bin/FileCheck --check-prefix=GFX942 /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
+ /b/ml-opt-devrel-x86-64-b1/build/bin/llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942
+ /b/ml-opt-devrel-x86-64-b1/build/bin/FileCheck --check-prefix=GFX942 /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
/b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll:219:16: error: GFX942-NEXT: is not on the line after the previous match
; GFX942-NEXT: v_mov_b32_e32 v16, 0
               ^
<stdin>:359:2: note: 'next' match was here
 v_mov_b32_e32 v16, 0
 ^
<stdin>:356:25: note: previous match ended here
 v_and_b32_e32 v0, 1, v0
                        ^
<stdin>:357:1: note: non-matching line after previous match is here
 v_cmp_eq_u32_e32 vcc, 1, v0
^

Input file: <stdin>
Check file: /b/ml-opt-devrel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
          .
          .
          .
        354: ; %bb.0: ; %entry 
        355:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 
        356:  v_and_b32_e32 v0, 1, v0 
        357:  v_cmp_eq_u32_e32 vcc, 1, v0 
        358:  v_mov_b32_e32 v15, 0 
        359:  v_mov_b32_e32 v16, 0 
next:219      !~~~~~~~~~~~~~~~~~~~  error: match on wrong line
        360:  v_mov_b32_e32 v1, 0 
        361:  v_mov_b32_e32 v2, 0 
        362:  v_mov_b32_e32 v3, 0 
        363:  v_mov_b32_e32 v17, 0 
        364:  v_mov_b32_e32 v5, 0 
          .
          .
          .
>>>>>>

--

...

@llvm-ci
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llvm-ci commented Mar 6, 2025

LLVM Buildbot has detected a new failure on builder ml-opt-dev-x86-64 running on ml-opt-dev-x86-64-b2 while building llvm at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/137/builds/14579

Here is the relevant piece of the build log for the reference 
Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/AMDGPU/masked-load-vectortypes.ll' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 2: /b/ml-opt-dev-x86-64-b1/build/bin/llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll | /b/ml-opt-dev-x86-64-b1/build/bin/FileCheck --check-prefix=GFX942 /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
+ /b/ml-opt-dev-x86-64-b1/build/bin/FileCheck --check-prefix=GFX942 /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
+ /b/ml-opt-dev-x86-64-b1/build/bin/llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942
/b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll:219:16: error: GFX942-NEXT: is not on the line after the previous match
; GFX942-NEXT: v_mov_b32_e32 v16, 0
               ^
<stdin>:359:2: note: 'next' match was here
 v_mov_b32_e32 v16, 0
 ^
<stdin>:356:25: note: previous match ended here
 v_and_b32_e32 v0, 1, v0
                        ^
<stdin>:357:1: note: non-matching line after previous match is here
 v_cmp_eq_u32_e32 vcc, 1, v0
^

Input file: <stdin>
Check file: /b/ml-opt-dev-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
          .
          .
          .
        354: ; %bb.0: ; %entry 
        355:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 
        356:  v_and_b32_e32 v0, 1, v0 
        357:  v_cmp_eq_u32_e32 vcc, 1, v0 
        358:  v_mov_b32_e32 v15, 0 
        359:  v_mov_b32_e32 v16, 0 
next:219      !~~~~~~~~~~~~~~~~~~~  error: match on wrong line
        360:  v_mov_b32_e32 v1, 0 
        361:  v_mov_b32_e32 v2, 0 
        362:  v_mov_b32_e32 v3, 0 
        363:  v_mov_b32_e32 v17, 0 
        364:  v_mov_b32_e32 v5, 0 
          .
          .
          .
>>>>>>

--

...

@JanekvO
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JanekvO commented Mar 6, 2025

Some buildbots are failing
Apologies, I keep forgetting that the premerge passes are without rebasing on top of current main branch. Will commit a NFC directly with updated checks.

@llvm-ci
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llvm-ci commented Mar 6, 2025

LLVM Buildbot has detected a new failure on builder ml-opt-rel-x86-64 running on ml-opt-rel-x86-64-b2 while building llvm at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/185/builds/14316

Here is the relevant piece of the build log for the reference 
Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/AMDGPU/masked-load-vectortypes.ll' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 2: /b/ml-opt-rel-x86-64-b1/build/bin/llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll | /b/ml-opt-rel-x86-64-b1/build/bin/FileCheck --check-prefix=GFX942 /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
+ /b/ml-opt-rel-x86-64-b1/build/bin/llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942
+ /b/ml-opt-rel-x86-64-b1/build/bin/FileCheck --check-prefix=GFX942 /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
/b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll:219:16: error: GFX942-NEXT: is not on the line after the previous match
; GFX942-NEXT: v_mov_b32_e32 v16, 0
               ^
<stdin>:359:2: note: 'next' match was here
 v_mov_b32_e32 v16, 0
 ^
<stdin>:356:25: note: previous match ended here
 v_and_b32_e32 v0, 1, v0
                        ^
<stdin>:357:1: note: non-matching line after previous match is here
 v_cmp_eq_u32_e32 vcc, 1, v0
^

Input file: <stdin>
Check file: /b/ml-opt-rel-x86-64-b1/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
          .
          .
          .
        354: ; %bb.0: ; %entry 
        355:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 
        356:  v_and_b32_e32 v0, 1, v0 
        357:  v_cmp_eq_u32_e32 vcc, 1, v0 
        358:  v_mov_b32_e32 v15, 0 
        359:  v_mov_b32_e32 v16, 0 
next:219      !~~~~~~~~~~~~~~~~~~~  error: match on wrong line
        360:  v_mov_b32_e32 v1, 0 
        361:  v_mov_b32_e32 v2, 0 
        362:  v_mov_b32_e32 v3, 0 
        363:  v_mov_b32_e32 v17, 0 
        364:  v_mov_b32_e32 v5, 0 
          .
          .
          .
>>>>>>

--

...

JanekvO added a commit to JanekvO/llvm-project that referenced this pull request Mar 6, 2025
@JanekvO
[AMDGPU][NFC] Update premerged test added in llvm#129703 to reflect u…
50f8a5e 
…pstream changes
JanekvO added a commit that referenced this pull request Mar 6, 2025
@JanekvO
[AMDGPU][NFC] Update premerged test from #129703 to reflect upstream (#…
37aad2c 
…130154)
@llvm-ci
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llvm-ci commented Mar 6, 2025

LLVM Buildbot has detected a new failure on builder premerge-monolithic-linux running on premerge-linux-1 while building llvm at step 7 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/153/builds/24870

Here is the relevant piece of the build log for the reference 
Step 7 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/AMDGPU/masked-load-vectortypes.ll' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 2: /build/buildbot/premerge-monolithic-linux/build/bin/llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < /build/buildbot/premerge-monolithic-linux/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll | /build/buildbot/premerge-monolithic-linux/build/bin/FileCheck --check-prefix=GFX942 /build/buildbot/premerge-monolithic-linux/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
+ /build/buildbot/premerge-monolithic-linux/build/bin/llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942
+ /build/buildbot/premerge-monolithic-linux/build/bin/FileCheck --check-prefix=GFX942 /build/buildbot/premerge-monolithic-linux/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
/build/buildbot/premerge-monolithic-linux/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll:219:16: error: GFX942-NEXT: is not on the line after the previous match
; GFX942-NEXT: v_mov_b32_e32 v16, 0
               ^
<stdin>:359:2: note: 'next' match was here
 v_mov_b32_e32 v16, 0
 ^
<stdin>:356:25: note: previous match ended here
 v_and_b32_e32 v0, 1, v0
                        ^
<stdin>:357:1: note: non-matching line after previous match is here
 v_cmp_eq_u32_e32 vcc, 1, v0
^

Input file: <stdin>
Check file: /build/buildbot/premerge-monolithic-linux/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
          .
          .
          .
        354: ; %bb.0: ; %entry 
        355:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 
        356:  v_and_b32_e32 v0, 1, v0 
        357:  v_cmp_eq_u32_e32 vcc, 1, v0 
        358:  v_mov_b32_e32 v15, 0 
        359:  v_mov_b32_e32 v16, 0 
next:219      !~~~~~~~~~~~~~~~~~~~  error: match on wrong line
        360:  v_mov_b32_e32 v1, 0 
        361:  v_mov_b32_e32 v2, 0 
        362:  v_mov_b32_e32 v3, 0 
        363:  v_mov_b32_e32 v17, 0 
        364:  v_mov_b32_e32 v5, 0 
          .
          .
          .
>>>>>>

--

...

@llvm-ci
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llvm-ci commented Mar 6, 2025

LLVM Buildbot has detected a new failure on builder lld-x86_64-ubuntu-fast running on as-builder-4 while building llvm at step 6 "test-build-unified-tree-check-all".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/33/builds/12531

Here is the relevant piece of the build log for the reference 
Step 6 (test-build-unified-tree-check-all) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/AMDGPU/masked-load-vectortypes.ll' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 2: /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/build/bin/llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll | /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/build/bin/FileCheck --check-prefix=GFX942 /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
+ /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/build/bin/FileCheck --check-prefix=GFX942 /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
+ /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/build/bin/llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942
/home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll:219:16: error: GFX942-NEXT: is not on the line after the previous match
; GFX942-NEXT: v_mov_b32_e32 v16, 0
               ^
<stdin>:359:2: note: 'next' match was here
 v_mov_b32_e32 v16, 0
 ^
<stdin>:356:25: note: previous match ended here
 v_and_b32_e32 v0, 1, v0
                        ^
<stdin>:357:1: note: non-matching line after previous match is here
 v_cmp_eq_u32_e32 vcc, 1, v0
^

Input file: <stdin>
Check file: /home/buildbot/worker/as-builder-4/ramdisk/lld-x86_64/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
          .
          .
          .
        354: ; %bb.0: ; %entry 
        355:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 
        356:  v_and_b32_e32 v0, 1, v0 
        357:  v_cmp_eq_u32_e32 vcc, 1, v0 
        358:  v_mov_b32_e32 v15, 0 
        359:  v_mov_b32_e32 v16, 0 
next:219      !~~~~~~~~~~~~~~~~~~~  error: match on wrong line
        360:  v_mov_b32_e32 v1, 0 
        361:  v_mov_b32_e32 v2, 0 
        362:  v_mov_b32_e32 v3, 0 
        363:  v_mov_b32_e32 v17, 0 
        364:  v_mov_b32_e32 v5, 0 
          .
          .
          .
>>>>>>

--

...

@llvm-ci
Copy link
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llvm-ci commented Mar 6, 2025

LLVM Buildbot has detected a new failure on builder llvm-x86_64-debian-dylib running on gribozavr4 while building llvm at step 7 "test-build-unified-tree-check-llvm".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/60/builds/21266

Here is the relevant piece of the build log for the reference 
Step 7 (test-build-unified-tree-check-llvm) failure: test (failure)
******************** TEST 'LLVM :: CodeGen/AMDGPU/masked-load-vectortypes.ll' FAILED ********************
Exit Code: 1

Command Output (stderr):
--
RUN: at line 2: /b/1/llvm-x86_64-debian-dylib/build/bin/llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < /b/1/llvm-x86_64-debian-dylib/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll | /b/1/llvm-x86_64-debian-dylib/build/bin/FileCheck --check-prefix=GFX942 /b/1/llvm-x86_64-debian-dylib/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
+ /b/1/llvm-x86_64-debian-dylib/build/bin/FileCheck --check-prefix=GFX942 /b/1/llvm-x86_64-debian-dylib/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll
+ /b/1/llvm-x86_64-debian-dylib/build/bin/llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942
/b/1/llvm-x86_64-debian-dylib/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll:219:16: error: GFX942-NEXT: is not on the line after the previous match
; GFX942-NEXT: v_mov_b32_e32 v16, 0
               ^
<stdin>:359:2: note: 'next' match was here
 v_mov_b32_e32 v16, 0
 ^
<stdin>:356:25: note: previous match ended here
 v_and_b32_e32 v0, 1, v0
                        ^
<stdin>:357:1: note: non-matching line after previous match is here
 v_cmp_eq_u32_e32 vcc, 1, v0
^

Input file: <stdin>
Check file: /b/1/llvm-x86_64-debian-dylib/llvm-project/llvm/test/CodeGen/AMDGPU/masked-load-vectortypes.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
          .
          .
          .
        354: ; %bb.0: ; %entry 
        355:  s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 
        356:  v_and_b32_e32 v0, 1, v0 
        357:  v_cmp_eq_u32_e32 vcc, 1, v0 
        358:  v_mov_b32_e32 v15, 0 
        359:  v_mov_b32_e32 v16, 0 
next:219      !~~~~~~~~~~~~~~~~~~~  error: match on wrong line
        360:  v_mov_b32_e32 v1, 0 
        361:  v_mov_b32_e32 v2, 0 
        362:  v_mov_b32_e32 v3, 0 
        363:  v_mov_b32_e32 v17, 0 
        364:  v_mov_b32_e32 v5, 0 
          .
          .
          .
>>>>>>

--

...

jph-13 pushed a commit to jph-13/llvm-project that referenced this pull request Mar 21, 2025
@JanekvO @jph-13
[AMDGPU] Masked load vectortype test (llvm#129703)
2f7ed04
jph-13 pushed a commit to jph-13/llvm-project that referenced this pull request Mar 21, 2025
@JanekvO @jph-13
[AMDGPU][NFC] Update premerged test from llvm#129703 to reflect upstr…
364ab74 
…eam (llvm#130154)
@JanekvO JanekvO mentioned this pull request May 7, 2025
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@arsenm arsenm arsenm approved these changes

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@JanekvO @llvmbot @llvm-ci @arsenm