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[Mips] Do not emit instruction teq if divisor is non-zero immediate value in FastISel implementation #135768

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Merged
merged 1 commit into from
Apr 25, 2025
Merged

[Mips] Do not emit instruction teq if divisor is non-zero immediate value in FastISel implementation #135768

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5 changes: 4 additions & 1 deletion llvm/lib/Target/Mips/MipsFastISel.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1947,7 +1947,10 @@ bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
return false;

emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
if (!isa<ConstantInt>(I->getOperand(1)) ||
dyn_cast<ConstantInt>(I->getOperand(1))->isZero()) {
emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
}

Register ResultReg = createResultReg(&Mips::GPR32RegClass);
if (!ResultReg)
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29 changes: 29 additions & 0 deletions llvm/test/CodeGen/Mips/Fast-ISel/div-imm.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,29 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic | FileCheck %s

define i32 @div_imm_non_zero(i32 signext %a) nounwind {
; CHECK-LABEL: div_imm_non_zero:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addiu $1, $zero, 1234
; CHECK-NEXT: div $zero, $4, $1
; CHECK-NEXT: mflo $2
; CHECK-NEXT: jr $ra
; CHECK-NEXT: nop
entry:
%div = sdiv i32 %a, 1234
ret i32 %div
}

define i32 @div_imm_zero(i32 signext %a) nounwind {
; CHECK-LABEL: div_imm_zero:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addiu $1, $zero, 0
; CHECK-NEXT: div $zero, $4, $zero
; CHECK-NEXT: teq $zero, $zero, 7
; CHECK-NEXT: mflo $2
; CHECK-NEXT: jr $ra
; CHECK-NEXT: nop
entry:
%div = sdiv i32 %a, 0
ret i32 %div
}
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