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[mlir][ArmSME] Add mask operand to store_tile_slice #70838

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Nov 2, 2023
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[mlir][ArmSME] Add mask operand to store_tile_slice #70838

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26bb905
[mlir][ArmSME] Add mask operand to store_tile_slice
c-rhodes Oct 15, 2023
6c2cf20
address comments
c-rhodes Nov 1, 2023
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40 changes: 24 additions & 16 deletions mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td
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Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,15 @@ class HasMatchingMaskTypeConstraint<string vector, string mask> :
vector, mask,
"::llvm::cast<mlir::VectorType>($_self).cloneWith({}, IntegerType::get($_ctxt, 1))">;

class TileSliceMaskConstraint<string tile, string mask> :
TypesMatchWith<
"`" # mask # "` has i1 element type and the shape is a slice of `" # tile # "`",
tile, mask,
"VectorType("
"VectorType::Builder("
"::llvm::cast<mlir::VectorType>($_self)"
").dropDim(0).setElementType(IntegerType::get($_self.getContext(), 1)))">;

//===----------------------------------------------------------------------===//
// ArmSME attr definitions
//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -408,15 +417,7 @@ def TileStoreOp : ArmSME_Op<"tile_store", [
}

def LoadTileSliceOp : ArmSME_Op<"load_tile_slice", [
AllTypesMatch<["tile", "result"]>,
TypesMatchWith<
"mask has i1 element type and is a slice of the result",
"result", "mask",
"VectorType("
"VectorType::Builder("
"::llvm::cast<mlir::VectorType>($_self)"
").dropDim(0).setElementType(IntegerType::get($_self.getContext(), 1))"
")">,
AllTypesMatch<["tile", "result"]>, TileSliceMaskConstraint<"result", "mask">
]> {
let summary = "Tile slice load and update operation";
let description = [{
Expand Down Expand Up @@ -474,7 +475,9 @@ def LoadTileSliceOp : ArmSME_Op<"load_tile_slice", [
}];
}

def StoreTileSliceOp : ArmSME_Op<"store_tile_slice"> {
def StoreTileSliceOp : ArmSME_Op<"store_tile_slice", [
TileSliceMaskConstraint<"tile", "mask">
]> {
let summary = "Tile slice store operation";
let description = [{
Stores a 1D tile slice from a 2D SME "virtual tile" into memory. The tile
Expand All @@ -489,22 +492,27 @@ def StoreTileSliceOp : ArmSME_Op<"store_tile_slice"> {
dimensions since the operation is scalable, and the element type must be a
scalar that matches the element type of the input tile.

An SSA value `mask` specifies to mask out elements written to the MemRef.
The `mask` type is an `i1` vector with a shape that matches how elements
are written to the MemRef.

Example 1: Store vector<[16]xi8> horizontal (default) tile slice from tile at given index to memory.
```mlir
arm_sme.store_tile_slice %tile, %tile_slice_index, %base[%c0] : vector<[16]x[16]xi8>, memref<?x?xi8>
arm_sme.store_tile_slice %tile, %tile_slice_index, %mask, %base[%c0] : vector<[16]x[16]xi8>, vector<[16]xi1>, memref<?x?xi8>
```

Example 2: Store vector<[4]xf32> vertical tile slice from tile at given index to memory.
```mlir
arm_sme.store_tile_slice %tile, %tile_slice_index, %base[%c0] layout<vertical> : vector<[4]x[4]xf32>, memref<?x?xf32>
arm_sme.store_tile_slice %tile, %tile_slice_index, %mask, %base[%c0] layout<vertical> : vector<[4]x[4]xf32>, vector<[4]xi1>, memref<?x?xf32>
```

Example 3: Store a vector<[1]xi128> vertical tile slice from tile at given index to memory.
```mlir
arm_sme.store_tile_slice %tile, %tile_slice_index, %base[%c0] layout<vertical> : vector<[1]x[1]xi128>, memref<?x?xi128>
arm_sme.store_tile_slice %tile, %tile_slice_index, %mask, %base[%c0] layout<vertical> : vector<[1]x[1]xi128>, vector<[1]xi1>, memref<?x?xi128>
```
}];
let arguments = (ins SMETile:$tile, Index:$tile_slice_index,
let arguments = (ins
SMETile:$tile, Index:$tile_slice_index, AnyVector:$mask,
Arg<AnyMemRef, "the reference to store to", [MemWrite]>:$base,
Variadic<Index>:$indices, ArmSME_TileSliceLayoutAttr:$layout
);
Expand All @@ -518,8 +526,8 @@ def StoreTileSliceOp : ArmSME_Op<"store_tile_slice"> {
}];

let assemblyFormat = [{
$tile `,` $tile_slice_index `,` $base `[` $indices `]` (`layout` `` $layout^)?
attr-dict `:` type($base) `,` type($tile)
$tile `,` $tile_slice_index `,` $mask `,` $base `[` $indices `]` (`layout` `` $layout^)?
attr-dict `:` type($base) `,` type($mask) `,` type($tile)
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Is this type($mask) needed? It should be inferred from your TileSliceMaskConstraint

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No it can be inferred as you say, but I decided to add the type anyway since this maps 1-1 with intrinsic. tile_load/tile_store are aligned with Vector transfer read/write so I didn't add mask type to asm for those.

The type is also present in load_tile_slice, we could remove in a follow-up if desired? I've don't mind either way.

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I prefer omitting the types that are very clear from context (i.e. the mask size must match the slice), but this is fine for now.

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Ok cool cheers, I'll post a follow-up :)

}];
}

Expand Down
9 changes: 8 additions & 1 deletion mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -190,14 +190,21 @@ struct TileStoreOpConversion : public OpRewritePattern<arm_sme::TileStoreOp> {

rewriter.setInsertionPointToStart(forOp.getBody());

// Create an 'all true' predicate for the tile slice.
auto predicateType =
VectorType::get(tileType.getDimSize(1), rewriter.getI1Type(), true);
auto allTruePredicate = rewriter.create<arith::ConstantOp>(
loc, DenseElementsAttr::get(predicateType, true));

SmallVector<Value> memrefIndices;
auto tileSliceIndex = forOp.getInductionVar();
getMemrefIndices(tileStoreOp.getIndices(),
tileStoreOp.getMemRefType().getRank(), tileSliceIndex,
numTileSlices, memrefIndices, loc, rewriter);
rewriter.replaceOpWithNewOp<arm_sme::StoreTileSliceOp>(
tileStoreOp, tileStoreOp.getValueToStore(), tileSliceIndex,
tileStoreOp.getBase(), memrefIndices, tileStoreOp.getLayout());
allTruePredicate, tileStoreOp.getBase(), memrefIndices,
tileStoreOp.getLayout());

return success();
}
Expand Down
28 changes: 11 additions & 17 deletions mlir/lib/Dialect/ArmSME/Transforms/LegalizeForLLVMExport.cpp
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Expand Up @@ -278,13 +278,7 @@ struct StoreTileSliceToArmSMELowering
auto tileSliceI32 = rewriter.create<arith::IndexCastUIOp>(
loc, rewriter.getI32Type(), tileSlice);

// Create all active predicate mask.
auto one = rewriter.create<arith::ConstantOp>(
loc, rewriter.getI1Type(),
rewriter.getIntegerAttr(rewriter.getI1Type(), 1));
auto predTy = VectorType::get(tileType.getShape()[0], rewriter.getI1Type(),
/*scalableDims=*/{true});
auto allActiveMask = rewriter.create<vector::SplatOp>(loc, predTy, one);
auto maskOp = storeTileSliceOp.getMask();

Value tileI32 = castTileIDToI32(tile, loc, rewriter);
arm_sme::TileSliceLayout layout = storeTileSliceOp.getLayout();
Expand All @@ -295,23 +289,23 @@ struct StoreTileSliceToArmSMELowering
llvm_unreachable("unexpected element type!");
case 8:
rewriter.replaceOpWithNewOp<arm_sme::aarch64_sme_st1b_horiz>(
storeTileSliceOp, allActiveMask, ptr, tileI32, tileSliceI32);
storeTileSliceOp, maskOp, ptr, tileI32, tileSliceI32);
break;
case 16:
rewriter.replaceOpWithNewOp<arm_sme::aarch64_sme_st1h_horiz>(
storeTileSliceOp, allActiveMask, ptr, tileI32, tileSliceI32);
storeTileSliceOp, maskOp, ptr, tileI32, tileSliceI32);
break;
case 32:
rewriter.replaceOpWithNewOp<arm_sme::aarch64_sme_st1w_horiz>(
storeTileSliceOp, allActiveMask, ptr, tileI32, tileSliceI32);
storeTileSliceOp, maskOp, ptr, tileI32, tileSliceI32);
break;
case 64:
rewriter.replaceOpWithNewOp<arm_sme::aarch64_sme_st1d_horiz>(
storeTileSliceOp, allActiveMask, ptr, tileI32, tileSliceI32);
storeTileSliceOp, maskOp, ptr, tileI32, tileSliceI32);
break;
case 128:
rewriter.replaceOpWithNewOp<arm_sme::aarch64_sme_st1q_horiz>(
storeTileSliceOp, allActiveMask, ptr, tileI32, tileSliceI32);
storeTileSliceOp, maskOp, ptr, tileI32, tileSliceI32);
break;
}
} else {
Expand All @@ -320,23 +314,23 @@ struct StoreTileSliceToArmSMELowering
llvm_unreachable("unexpected element type!");
case 8:
rewriter.replaceOpWithNewOp<arm_sme::aarch64_sme_st1b_vert>(
storeTileSliceOp, allActiveMask, ptr, tileI32, tileSliceI32);
storeTileSliceOp, maskOp, ptr, tileI32, tileSliceI32);
break;
case 16:
rewriter.replaceOpWithNewOp<arm_sme::aarch64_sme_st1h_vert>(
storeTileSliceOp, allActiveMask, ptr, tileI32, tileSliceI32);
storeTileSliceOp, maskOp, ptr, tileI32, tileSliceI32);
break;
case 32:
rewriter.replaceOpWithNewOp<arm_sme::aarch64_sme_st1w_vert>(
storeTileSliceOp, allActiveMask, ptr, tileI32, tileSliceI32);
storeTileSliceOp, maskOp, ptr, tileI32, tileSliceI32);
break;
case 64:
rewriter.replaceOpWithNewOp<arm_sme::aarch64_sme_st1d_vert>(
storeTileSliceOp, allActiveMask, ptr, tileI32, tileSliceI32);
storeTileSliceOp, maskOp, ptr, tileI32, tileSliceI32);
break;
case 128:
rewriter.replaceOpWithNewOp<arm_sme::aarch64_sme_st1q_vert>(
storeTileSliceOp, allActiveMask, ptr, tileI32, tileSliceI32);
storeTileSliceOp, maskOp, ptr, tileI32, tileSliceI32);
break;
}
}
Expand Down
3 changes: 2 additions & 1 deletion mlir/test/Conversion/ArmSMEToSCF/arm-sme-to-scf.mlir
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Expand Up @@ -48,8 +48,9 @@ func.func @arm_sme_tile_load_ver(%src : memref<?x?xi32>) {
// CHECK-DAG: %[[VSCALE:.*]] = vector.vscale
// CHECK: %[[NUM_TILE_SLICES:.*]] = arith.muli %[[C4]], %[[VSCALE]] : index
// CHECK: scf.for %[[TILE_SLICE_INDEX:.*]] = %[[C0]] to %[[NUM_TILE_SLICES]] step %[[C1]] {
// CHECK: %[[PTRUE_S:.*]] = arith.constant dense<true> : vector<[4]xi1>
// CHECK: %[[OFFSET:.*]] = arith.addi %[[C0]], %[[TILE_SLICE_INDEX]] : index
// CHECK: arm_sme.store_tile_slice %[[TILE]], %[[TILE_SLICE_INDEX]], %[[DEST]]{{\[}}%[[OFFSET]], %[[C0]]] : memref<?x?xi32>, vector<[4]x[4]xi32>
// CHECK: arm_sme.store_tile_slice %[[TILE]], %[[TILE_SLICE_INDEX]], %[[PTRUE_S]], %[[DEST]]{{\[}}%[[OFFSET]], %[[C0]]] : memref<?x?xi32>, vector<[4]xi1>, vector<[4]x[4]xi32>
func.func @arm_sme_tile_store_hor(%tile : vector<[4]x[4]xi32>, %dest : memref<?x?xi32>) {
%c0 = arith.constant 0 : index
arm_sme.tile_store %tile, %dest[%c0, %c0] : memref<?x?xi32>, vector<[4]x[4]xi32>
Expand Down
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