Skip to content

[M68k] Emit RTE for interrupt handler. #72787

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Dec 4, 2023
Merged

Conversation

0x59616e
Copy link
Contributor

Fixes #64833

@llvmbot
Copy link
Member

llvmbot commented Nov 19, 2023

@llvm/pr-subscribers-backend-m68k

Author: Sheng (0x59616e)

Changes

Fixes #64833


Full diff: https://github.com/llvm/llvm-project/pull/72787.diff

3 Files Affected:

  • (modified) llvm/lib/Target/M68k/M68kExpandPseudo.cpp (+5-6)
  • (modified) llvm/lib/Target/M68k/M68kInstrControl.td (+4)
  • (added) llvm/test/CodeGen/M68k/CConv/rte.ll (+11)
diff --git a/llvm/lib/Target/M68k/M68kExpandPseudo.cpp b/llvm/lib/Target/M68k/M68kExpandPseudo.cpp
index 13268d754a9dde6..7bd3821077737ea 100644
--- a/llvm/lib/Target/M68k/M68kExpandPseudo.cpp
+++ b/llvm/lib/Target/M68k/M68kExpandPseudo.cpp
@@ -252,12 +252,11 @@ bool M68kExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
     return true;
   }
   case M68k::RET: {
-    // Adjust stack to erase error code
-    int64_t StackAdj = MBBI->getOperand(0).getImm();
-    MachineInstrBuilder MIB;
-
-    if (StackAdj == 0) {
-      MIB = BuildMI(MBB, MBBI, DL, TII->get(M68k::RTS));
+    if (MBB.getParent()->getFunction().getCallingConv() ==
+        CallingConv::M68k_INTR) {
+      BuildMI(MBB, MBBI, DL, TII->get(M68k::RTE));
+    } else if (int64_t StackAdj = MBBI->getOperand(0).getImm(); StackAdj == 0) {
+      BuildMI(MBB, MBBI, DL, TII->get(M68k::RTS));
     } else {
       // Copy return address from stack to a free address(A0 or A1) register
       // TODO check if pseudo expand uses free address register
diff --git a/llvm/lib/Target/M68k/M68kInstrControl.td b/llvm/lib/Target/M68k/M68kInstrControl.td
index 225f932f3316691..6e116d7cfe40193 100644
--- a/llvm/lib/Target/M68k/M68kInstrControl.td
+++ b/llvm/lib/Target/M68k/M68kInstrControl.td
@@ -327,6 +327,10 @@ def RTS : MxInst<(outs), (ins), "rts", []> {
   let Inst = (descend 0b0100, 0b1110, 0b0111, 0b0101);
 }
 
+def RTE: MxInst<(outs), (ins), "rte", []> {
+  let Inst = (descend 0b0100, 0b1110, 0b0111, 0b0011);
+}
+
 let isCodeGenOnly = 1 in
 def RET : MxPseudo<(outs), (ins i32imm:$adj, variable_ops),
                    [(MxRet timm:$adj)]>;
diff --git a/llvm/test/CodeGen/M68k/CConv/rte.ll b/llvm/test/CodeGen/M68k/CConv/rte.ll
new file mode 100644
index 000000000000000..da7eb1bdc70e772
--- /dev/null
+++ b/llvm/test/CodeGen/M68k/CConv/rte.ll
@@ -0,0 +1,11 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -mtriple m68k -o - %s | FileCheck %s
+
+define cc101 void @interrupt_handler() {
+; CHECK-LABEL: interrupt_handler:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  ; %bb.0: ; %entry
+; CHECK-NEXT:    rte
+entry:
+  ret void
+}

@glaubitz
Copy link
Contributor

CC @thankfulmachine You may want to test this patch whether it addresses the original issue.

@glaubitz
Copy link
Contributor

@mshockwave Any comment? I will test the changes later.

Copy link
Member

@mshockwave mshockwave left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LGTM thanks for fixing this!

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple m68k -o - %s | FileCheck %s

define cc101 void @interrupt_handler() {
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

just a note for future us: we should probably give this CC a more descriptive name.

@0x59616e 0x59616e merged commit 725656b into llvm:main Dec 4, 2023
@0x59616e 0x59616e deleted the pr64833 branch December 4, 2023 07:11
if (MBB.getParent()->getFunction().getCallingConv() ==
CallingConv::M68k_INTR) {
BuildMI(MBB, MBBI, DL, TII->get(M68k::RTE));
} else if (int64_t StackAdj = MBBI->getOperand(0).getImm(); StackAdj == 0) {
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Why not just } else if (MBBI->getOperand(0).getImm() == 0) { ?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Oh, such a blunder.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Development

Successfully merging this pull request may close these issues.

[M68k] RTE instruction missing
5 participants