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[M68k] Emit RTE for interrupt handler. #72787

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Merged
merged 1 commit into from
Dec 4, 2023
Merged

[M68k] Emit RTE for interrupt handler. #72787

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11 changes: 5 additions & 6 deletions llvm/lib/Target/M68k/M68kExpandPseudo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -252,12 +252,11 @@ bool M68kExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
return true;
}
case M68k::RET: {
// Adjust stack to erase error code
int64_t StackAdj = MBBI->getOperand(0).getImm();
MachineInstrBuilder MIB;

if (StackAdj == 0) {
MIB = BuildMI(MBB, MBBI, DL, TII->get(M68k::RTS));
if (MBB.getParent()->getFunction().getCallingConv() ==
CallingConv::M68k_INTR) {
BuildMI(MBB, MBBI, DL, TII->get(M68k::RTE));
} else if (int64_t StackAdj = MBBI->getOperand(0).getImm(); StackAdj == 0) {
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Why not just } else if (MBBI->getOperand(0).getImm() == 0) { ?

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Oh, such a blunder.

BuildMI(MBB, MBBI, DL, TII->get(M68k::RTS));
} else {
// Copy return address from stack to a free address(A0 or A1) register
// TODO check if pseudo expand uses free address register
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4 changes: 4 additions & 0 deletions llvm/lib/Target/M68k/M68kInstrControl.td
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Expand Up @@ -327,6 +327,10 @@ def RTS : MxInst<(outs), (ins), "rts", []> {
let Inst = (descend 0b0100, 0b1110, 0b0111, 0b0101);
}

def RTE: MxInst<(outs), (ins), "rte", []> {
let Inst = (descend 0b0100, 0b1110, 0b0111, 0b0011);
}

let isCodeGenOnly = 1 in
def RET : MxPseudo<(outs), (ins i32imm:$adj, variable_ops),
[(MxRet timm:$adj)]>;
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11 changes: 11 additions & 0 deletions llvm/test/CodeGen/M68k/CConv/rte.ll
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@@ -0,0 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple m68k -o - %s | FileCheck %s

define cc101 void @interrupt_handler() {
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just a note for future us: we should probably give this CC a more descriptive name.

; CHECK-LABEL: interrupt_handler:
; CHECK: .cfi_startproc
; CHECK-NEXT: ; %bb.0: ; %entry
; CHECK-NEXT: rte
entry:
ret void
}