[lldb][RISCV] Add RegisterContextPOSIXCore for RISC-V 64 #93297
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@llvm/pr-subscribers-lldb Author: Alexey Merzlyakov (AlexeyMerzlyakov) ChangesThe PR adds the support of CoreDump debugging for RISC-V 64. It implements new Also, the contribution fixes The patch was tested (on coredumps generated for simple Integer/FP calculation code) for cross x86_64 -> RISCV and native RISCV LLDB builds. There were performed basic LLDB functionality tests, such as:
Full diff: https://github.com/llvm/llvm-project/pull/93297.diff 5 Files Affected:
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
index 1834a94dc0260..035ce00e11626 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
@@ -58,7 +58,7 @@ RegisterContextPOSIX_riscv64::GetRegisterInfoAtIndex(size_t reg) {
}
size_t RegisterContextPOSIX_riscv64::GetRegisterSetCount() {
- return m_register_info_up->GetRegisterCount();
+ return m_register_info_up->GetRegisterSetCount();
}
const lldb_private::RegisterSet *
diff --git a/lldb/source/Plugins/Process/elf-core/CMakeLists.txt b/lldb/source/Plugins/Process/elf-core/CMakeLists.txt
index 8ddc671e3ae66..72925c835b5c8 100644
--- a/lldb/source/Plugins/Process/elf-core/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/elf-core/CMakeLists.txt
@@ -9,6 +9,7 @@ add_lldb_library(lldbPluginProcessElfCore PLUGIN
RegisterContextPOSIXCore_ppc64le.cpp
RegisterContextPOSIXCore_s390x.cpp
RegisterContextPOSIXCore_x86_64.cpp
+ RegisterContextPOSIXCore_riscv64.cpp
RegisterUtilities.cpp
LINK_LIBS
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
new file mode 100644
index 0000000000000..b0fd065e7cc62
--- /dev/null
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
@@ -0,0 +1,84 @@
+//===-- RegisterContextCorePOSIX_riscv64.cpp ------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "RegisterContextPOSIXCore_riscv64.h"
+
+#include "lldb/Utility/DataBufferHeap.h"
+
+using namespace lldb_private;
+
+std::unique_ptr<RegisterContextCorePOSIX_riscv64>
+RegisterContextCorePOSIX_riscv64::Create(
+ lldb_private::Thread &thread, const lldb_private::ArchSpec &arch,
+ const lldb_private::DataExtractor &gpregset,
+ llvm::ArrayRef<lldb_private::CoreNote> notes) {
+ Flags flags = 0;
+
+ auto register_info_up =
+ std::make_unique<RegisterInfoPOSIX_riscv64>(arch, flags);
+ return std::unique_ptr<RegisterContextCorePOSIX_riscv64>(
+ new RegisterContextCorePOSIX_riscv64(thread, std::move(register_info_up),
+ gpregset, notes));
+}
+
+RegisterContextCorePOSIX_riscv64::RegisterContextCorePOSIX_riscv64(
+ Thread &thread, std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info,
+ const DataExtractor &gpregset, llvm::ArrayRef<CoreNote> notes)
+ : RegisterContextPOSIX_riscv64(thread, std::move(register_info)) {
+
+ m_gpr_buffer = std::make_shared<DataBufferHeap>(gpregset.GetDataStart(),
+ gpregset.GetByteSize());
+ m_gpr.SetData(m_gpr_buffer);
+ m_gpr.SetByteOrder(gpregset.GetByteOrder());
+
+ ArchSpec arch = m_register_info_up->GetTargetArchitecture();
+ DataExtractor fpregset = getRegset(notes, arch.GetTriple(), FPR_Desc);
+ m_fpr_buffer = std::make_shared<DataBufferHeap>(fpregset.GetDataStart(),
+ fpregset.GetByteSize());
+ m_fpr.SetData(m_fpr_buffer);
+ m_fpr.SetByteOrder(fpregset.GetByteOrder());
+}
+
+RegisterContextCorePOSIX_riscv64::~RegisterContextCorePOSIX_riscv64() = default;
+
+bool RegisterContextCorePOSIX_riscv64::ReadGPR() { return true; }
+
+bool RegisterContextCorePOSIX_riscv64::ReadFPR() { return true; }
+
+bool RegisterContextCorePOSIX_riscv64::WriteGPR() {
+ assert(0);
+ return false;
+}
+
+bool RegisterContextCorePOSIX_riscv64::WriteFPR() {
+ assert(0);
+ return false;
+}
+
+bool RegisterContextCorePOSIX_riscv64::ReadRegister(
+ const RegisterInfo *reg_info, RegisterValue &value) {
+ const uint8_t *src = nullptr;
+ lldb::offset_t offset = reg_info->byte_offset;
+
+ if (IsGPR(reg_info->kinds[lldb::eRegisterKindLLDB])) {
+ src = m_gpr.GetDataStart();
+ } else { // IsFPR
+ src = m_fpr.GetDataStart();
+ offset -= GetGPRSize();
+ }
+
+ Status error;
+ value.SetFromMemoryData(*reg_info, src + offset, reg_info->byte_size,
+ lldb::eByteOrderLittle, error);
+ return error.Success();
+}
+
+bool RegisterContextCorePOSIX_riscv64::WriteRegister(
+ const RegisterInfo *reg_info, const RegisterValue &value) {
+ return false;
+}
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
new file mode 100644
index 0000000000000..3cf9531df2c1d
--- /dev/null
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
@@ -0,0 +1,60 @@
+//===-- RegisterContextPOSIXCore_riscv64.h ----------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV64_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV64_H
+
+#include "Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
+
+#include "Plugins/Process/elf-core/RegisterUtilities.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/DataExtractor.h"
+#include "lldb/Utility/RegisterValue.h"
+
+#include <memory>
+
+class RegisterContextCorePOSIX_riscv64 : public RegisterContextPOSIX_riscv64 {
+public:
+ static std::unique_ptr<RegisterContextCorePOSIX_riscv64>
+ Create(lldb_private::Thread &thread, const lldb_private::ArchSpec &arch,
+ const lldb_private::DataExtractor &gpregset,
+ llvm::ArrayRef<lldb_private::CoreNote> notes);
+
+ ~RegisterContextCorePOSIX_riscv64() override;
+
+ bool ReadRegister(const lldb_private::RegisterInfo *reg_info,
+ lldb_private::RegisterValue &value) override;
+
+ bool WriteRegister(const lldb_private::RegisterInfo *reg_info,
+ const lldb_private::RegisterValue &value) override;
+
+protected:
+ RegisterContextCorePOSIX_riscv64(
+ lldb_private::Thread &thread,
+ std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info,
+ const lldb_private::DataExtractor &gpregset,
+ llvm::ArrayRef<lldb_private::CoreNote> notes);
+
+ bool ReadGPR() override;
+
+ bool ReadFPR() override;
+
+ bool WriteGPR() override;
+
+ bool WriteFPR() override;
+
+private:
+ lldb::DataBufferSP m_gpr_buffer;
+ lldb::DataBufferSP m_fpr_buffer;
+
+ lldb_private::DataExtractor m_gpr;
+ lldb_private::DataExtractor m_fpr;
+};
+
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV64_H
diff --git a/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp b/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
index 3ce2a4a5c3fa4..2a83163884e16 100644
--- a/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
+++ b/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
@@ -35,6 +35,7 @@
#include "RegisterContextPOSIXCore_mips64.h"
#include "RegisterContextPOSIXCore_powerpc.h"
#include "RegisterContextPOSIXCore_ppc64le.h"
+#include "RegisterContextPOSIXCore_riscv64.h"
#include "RegisterContextPOSIXCore_s390x.h"
#include "RegisterContextPOSIXCore_x86_64.h"
#include "ThreadElfCore.h"
@@ -168,7 +169,8 @@ ThreadElfCore::CreateRegisterContextForFrame(StackFrame *frame) {
}
if (!reg_interface && arch.GetMachine() != llvm::Triple::aarch64 &&
- arch.GetMachine() != llvm::Triple::arm) {
+ arch.GetMachine() != llvm::Triple::arm &&
+ arch.GetMachine() != llvm::Triple::riscv64) {
LLDB_LOGF(log, "elf-core::%s:: Architecture(%d) or OS(%d) not supported",
__FUNCTION__, arch.GetMachine(), arch.GetTriple().getOS());
assert(false && "Architecture or OS not supported");
@@ -184,6 +186,10 @@ ThreadElfCore::CreateRegisterContextForFrame(StackFrame *frame) {
*this, std::make_unique<RegisterInfoPOSIX_arm>(arch), m_gpregset_data,
m_notes);
break;
+ case llvm::Triple::riscv64:
+ m_thread_reg_ctx_sp = RegisterContextCorePOSIX_riscv64::Create(
+ *this, arch, m_gpregset_data, m_notes);
+ break;
case llvm::Triple::mipsel:
case llvm::Triple::mips:
m_thread_reg_ctx_sp = std::make_shared<RegisterContextCorePOSIX_mips64>(
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Fix GetRegisterSetCount() method name misprint for RegisterContextPOSIX_riscv64
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lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
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This looks good to me, I'd like to see the std::make_unique in RegisterContextCorePOSIX_riscv64::Create and a sanity check for fetching the fpr, but maybe that's just unnecessary I don't work with RV64 targets myself, if you're comfortable with it as-is, that's fine.
lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
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This patch look good to me, do you have necessary permissions to squash & merge? |
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No, I have no rights to do this |
lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
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DavidSpickett
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Corefiles can be debugged anywhere, so you should add a test case to There is a way to minimise the size of the core file, see https://man7.org/linux/man-pages/man5/core.5.html "Controlling which mappings are written to the core dump". I usually generate a normal core, then keep removing stuff until the tests stop passing. Sometimes there's not much we can remove. |
Add RISC-V 64 testcases to TestLinuxCore.py
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I've added two testcases (one general and one checking main RISC-V registers) to |
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Thanks, these look good. This does not include the FP registers, but I'm ok with you adding proper testing (with inline asm to set the registers) later, in the register class refactoring you mentioned. For now, if the core has them, please add checks for the FPU registers (even if they're all 0, it's something at least). If it doesn't contain FPU regs then no worries, the PR is fine as is. |
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✅ With the latest revision this PR passed the Python code formatter. |
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Not sure I agree with the formatter here but we must bow to it regardless :) Please fix the formatting and then I'll merge this. Thanks for the contribution! |
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Oops, I've checked it with flake8, but did not have an idea about the darker tool. Fixed in latest commit. Thank you! |
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Yeah we settled on https://github.com/psf/black as the formatter, but that itself didn't have a way to format the contents of a commit. So "darker" is black but it can do that. |
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@AlexeyMerzlyakov Congratulations on having your first Pull Request (PR) merged into the LLVM Project! Your changes will be combined with recent changes from other authors, then tested Please check whether problems have been caused by your change specifically, as How to do this, and the rest of the post-merge process, is covered in detail here. If your change does cause a problem, it may be reverted, or you can revert it yourself. If you don't get any reports, no action is required from you. Your changes are working as expected, well done! |
The PR adds the support of CoreDump debugging for RISC-V 64. It implements new
RegisterContextCorePOSIX_riscv64class.Also, the contribution fixes
GetRegisterCount()->GetRegisterSetCount()misprint inRegisterContextPOSIX_riscv64::GetRegisterSetCount()method, which leaded toset && "Register set should be valid."assertion duringregister info aXcommand call.The patch was tested (on coredumps generated for simple Integer/FP calculation code) for cross x86_64 -> RISCV and native RISCV LLDB builds. There were performed basic LLDB functionality tests, such as: