Make Clippy happy.

src/itm.rs

@@ -28,6 +28,8 @@ impl<'p> fmt::Write for Port<'p> {
 }
 
 /// Writes a `buffer` to the ITM `port`
+#[allow(clippy::cast_ptr_alignment)]
+#[allow(clippy::transmute_ptr_to_ptr)]
 pub fn write_all(port: &mut Stim, buffer: &[u8]) {
     unsafe {
         let mut len = buffer.len();
@@ -86,6 +88,8 @@ pub fn write_all(port: &mut Stim, buffer: &[u8]) {
 /// // Or equivalently
 /// itm::write_aligned(&itm.stim[0], &Aligned(*b"Hello, world!\n"));
 /// ```
+#[allow(clippy::cast_ptr_alignment)]
+#[allow(clippy::transmute_ptr_to_ptr)]
 pub fn write_aligned(port: &mut Stim, buffer: &Aligned<A4, [u8]>) {
     unsafe {
         let len = buffer.len();
@@ -102,7 +106,7 @@ pub fn write_aligned(port: &mut Stim, buffer: &Aligned<A4, [u8]>) {
 
         // 3 bytes or less left
         let mut left = len & 0b11;
-        let mut ptr = buffer.as_ptr().offset(split as isize);
+        let mut ptr = buffer.as_ptr().add(split);
 
         // at least 2 bytes left
         if left > 1 {

src/lib.rs

@@ -32,6 +32,7 @@
 #![cfg_attr(feature = "inline-asm", feature(asm))]
 #![deny(missing_docs)]
 #![no_std]
+#![allow(clippy::identity_op)]
 
 extern crate aligned;
 extern crate bare_metal;

src/peripheral/cbp.rs

@@ -78,8 +78,8 @@ impl CBP {
         // CMSIS-Core implementation and use fixed values.
         unsafe {
             self.dcisw.write(
-                (((way as u32) & (CBP_SW_WAY_MASK >> CBP_SW_WAY_POS)) << CBP_SW_WAY_POS)
-                    | (((set as u32) & (CBP_SW_SET_MASK >> CBP_SW_SET_POS)) << CBP_SW_SET_POS),
+                ((u32::from(way) & (CBP_SW_WAY_MASK >> CBP_SW_WAY_POS)) << CBP_SW_WAY_POS)
+                    | ((u32::from(set) & (CBP_SW_SET_MASK >> CBP_SW_SET_POS)) << CBP_SW_SET_POS),
             );
         }
     }
@@ -108,8 +108,8 @@ impl CBP {
         // See comment for dcisw() about the format here
         unsafe {
             self.dccsw.write(
-                (((way as u32) & (CBP_SW_WAY_MASK >> CBP_SW_WAY_POS)) << CBP_SW_WAY_POS)
-                    | (((set as u32) & (CBP_SW_SET_MASK >> CBP_SW_SET_POS)) << CBP_SW_SET_POS),
+                ((u32::from(way) & (CBP_SW_WAY_MASK >> CBP_SW_WAY_POS)) << CBP_SW_WAY_POS)
+                    | ((u32::from(set) & (CBP_SW_SET_MASK >> CBP_SW_SET_POS)) << CBP_SW_SET_POS),
             );
         }
     }
@@ -130,8 +130,8 @@ impl CBP {
         // See comment for dcisw() about the format here
         unsafe {
             self.dccisw.write(
-                (((way as u32) & (CBP_SW_WAY_MASK >> CBP_SW_WAY_POS)) << CBP_SW_WAY_POS)
-                    | (((set as u32) & (CBP_SW_SET_MASK >> CBP_SW_SET_POS)) << CBP_SW_SET_POS),
+                ((u32::from(way) & (CBP_SW_WAY_MASK >> CBP_SW_WAY_POS)) << CBP_SW_WAY_POS)
+                    | ((u32::from(set) & (CBP_SW_SET_MASK >> CBP_SW_SET_POS)) << CBP_SW_SET_POS),
             );
         }
     }

src/peripheral/cpuid.rs

@@ -90,7 +90,7 @@ impl CPUID {
 
         unsafe {
             self.csselr.write(
-                (((level as u32) << CSSELR_LEVEL_POS) & CSSELR_LEVEL_MASK)
+                ((u32::from(level) << CSSELR_LEVEL_POS) & CSSELR_LEVEL_MASK)
                     | (((ind as u32) << CSSELR_IND_POS) & CSSELR_IND_MASK),
             )
         }

src/peripheral/nvic.rs

@@ -90,7 +90,7 @@ impl NVIC {
         let nr = interrupt.nr();
 
         unsafe {
-            self.stir.write(nr as u32);
+            self.stir.write(u32::from(nr));
         }
     }
 

src/peripheral/scb.rs

@@ -230,8 +230,8 @@ impl Exception {
     /// Returns the IRQ number of this `Exception`
     ///
     /// The return value is always within the closed range `[-1, -14]`
-    pub fn irqn(&self) -> i8 {
-        match *self {
+    pub fn irqn(self) -> i8 {
+        match self {
             Exception::NonMaskableInt => -14,
             Exception::HardFault => -13,
             #[cfg(not(armv6m))]
@@ -709,7 +709,6 @@ impl SCB {
 }
 
 /// System handlers, exceptions with configurable priority
-#[allow(non_camel_case_types)]
 #[derive(Clone, Copy, Debug, Eq, PartialEq)]
 pub enum SystemHandler {
     // NonMaskableInt, // priority is fixed
@@ -745,8 +744,8 @@ pub enum SystemHandler {
 }
 
 impl SystemHandler {
-    fn index(&self) -> u8 {
-        match *self {
+    fn index(self) -> u8 {
+        match self {
             #[cfg(not(armv6m))]
             SystemHandler::MemoryManagement => 4,
             #[cfg(not(armv6m))]

src/peripheral/syst.rs

@@ -26,7 +26,7 @@ pub enum SystClkSource {
     External,
 }
 
-const SYST_COUNTER_MASK: u32 = 0x00ffffff;
+const SYST_COUNTER_MASK: u32 = 0x00ff_ffff;
 
 const SYST_CSR_ENABLE: u32 = 1 << 0;
 const SYST_CSR_TICKINT: u32 = 1 << 1;
@@ -81,10 +81,10 @@ impl SYST {
     /// bit that indicates that the timer has wrapped (cf. `SYST.has_wrapped`)
     pub fn get_clock_source(&mut self) -> SystClkSource {
         // NOTE(unsafe) atomic read with no side effects
-        let clk_source_bit = self.csr.read() & SYST_CSR_CLKSOURCE != 0;
-        match clk_source_bit {
-            false => SystClkSource::External,
-            true => SystClkSource::Core,
+        if self.csr.read() & SYST_CSR_CLKSOURCE != 0 {
+            SystClkSource::Core
+        } else {
+            SystClkSource::External
         }
     }
 

src/register/apsr.rs

@@ -8,32 +8,32 @@ pub struct Apsr {
 
 impl Apsr {
     /// Returns the contents of the register as raw bits
-    pub fn bits(&self) -> u32 {
+    pub fn bits(self) -> u32 {
         self.bits
     }
 
     /// DSP overflow and saturation flag
-    pub fn q(&self) -> bool {
+    pub fn q(self) -> bool {
         self.bits & (1 << 27) == (1 << 27)
     }
 
     /// Overflow flag
-    pub fn v(&self) -> bool {
+    pub fn v(self) -> bool {
         self.bits & (1 << 28) == (1 << 28)
     }
 
     /// Carry or borrow flag
-    pub fn c(&self) -> bool {
+    pub fn c(self) -> bool {
         self.bits & (1 << 29) == (1 << 29)
     }
 
     /// Zero flag
-    pub fn z(&self) -> bool {
+    pub fn z(self) -> bool {
         self.bits & (1 << 30) == (1 << 30)
     }
 
     /// Negative flag
-    pub fn n(&self) -> bool {
+    pub fn n(self) -> bool {
         self.bits & (1 << 31) == (1 << 31)
     }
 }

src/register/control.rs

@@ -15,13 +15,13 @@ impl Control {
 
     /// Returns the contents of the register as raw bits
     #[inline]
-    pub fn bits(&self) -> u32 {
+    pub fn bits(self) -> u32 {
         self.bits
     }
 
     /// Thread mode privilege level
     #[inline]
-    pub fn npriv(&self) -> Npriv {
+    pub fn npriv(self) -> Npriv {
         if self.bits & (1 << 0) == (1 << 0) {
             Npriv::Unprivileged
         } else {
@@ -41,7 +41,7 @@ impl Control {
 
     /// Currently active stack pointer
     #[inline]
-    pub fn spsel(&self) -> Spsel {
+    pub fn spsel(self) -> Spsel {
         if self.bits & (1 << 1) == (1 << 1) {
             Spsel::Psp
         } else {
@@ -61,7 +61,7 @@ impl Control {
 
     /// Whether context floating-point is currently active
     #[inline]
-    pub fn fpca(&self) -> Fpca {
+    pub fn fpca(self) -> Fpca {
         if self.bits & (1 << 2) == (1 << 2) {
             Fpca::Active
         } else {
@@ -92,14 +92,14 @@ pub enum Npriv {
 impl Npriv {
     /// Is in privileged thread mode?
     #[inline]
-    pub fn is_privileged(&self) -> bool {
-        *self == Npriv::Privileged
+    pub fn is_privileged(self) -> bool {
+        self == Npriv::Privileged
     }
 
     /// Is in unprivileged thread mode?
     #[inline]
-    pub fn is_unprivileged(&self) -> bool {
-        *self == Npriv::Unprivileged
+    pub fn is_unprivileged(self) -> bool {
+        self == Npriv::Unprivileged
     }
 }
 
@@ -115,14 +115,14 @@ pub enum Spsel {
 impl Spsel {
     /// Is MSP the current stack pointer?
     #[inline]
-    pub fn is_msp(&self) -> bool {
-        *self == Spsel::Msp
+    pub fn is_msp(self) -> bool {
+        self == Spsel::Msp
     }
 
     /// Is PSP the current stack pointer?
     #[inline]
-    pub fn is_psp(&self) -> bool {
-        *self == Spsel::Psp
+    pub fn is_psp(self) -> bool {
+        self == Spsel::Psp
     }
 }
 
@@ -138,14 +138,14 @@ pub enum Fpca {
 impl Fpca {
     /// Is a floating-point context active?
     #[inline]
-    pub fn is_active(&self) -> bool {
-        *self == Fpca::Active
+    pub fn is_active(self) -> bool {
+        self == Fpca::Active
     }
 
     /// Is a floating-point context not active?
     #[inline]
-    pub fn is_not_active(&self) -> bool {
-        *self == Fpca::NotActive
+    pub fn is_not_active(self) -> bool {
+        self == Fpca::NotActive
     }
 }
 

src/register/faultmask.rs

@@ -11,13 +11,13 @@ pub enum Faultmask {
 
 impl Faultmask {
     /// All exceptions are active
-    pub fn is_active(&self) -> bool {
-        *self == Faultmask::Active
+    pub fn is_active(self) -> bool {
+        self == Faultmask::Active
     }
 
     /// All exceptions, except for NMI, are inactive
-    pub fn is_inactive(&self) -> bool {
-        *self == Faultmask::Inactive
+    pub fn is_inactive(self) -> bool {
+        self == Faultmask::Inactive
     }
 }
 

src/register/primask.rs

@@ -11,13 +11,13 @@ pub enum Primask {
 
 impl Primask {
     /// All exceptions with configurable priority are active
-    pub fn is_active(&self) -> bool {
-        *self == Primask::Active
+    pub fn is_active(self) -> bool {
+        self == Primask::Active
     }
 
     /// All exceptions with configurable priority are inactive
-    pub fn is_inactive(&self) -> bool {
-        *self == Primask::Inactive
+    pub fn is_inactive(self) -> bool {
+        self == Primask::Inactive
     }
 }